1. Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of silicon on insulator (SOI) devices and more particularly to a method for fabricating complementary silicon on insulator (CSOI) devices that can be partially depleted and fully depleted using wafer bonding and more particularly to a method for forming optional air gaps in insulating regions in silicon on insulator (SOI) devices.
2. Description of the Prior Art
Integrated circuits (ICs) include a multitude of transistors formed on a semiconductor substrate. Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices.
The removal of portions of the first substrate can comprises a grinding process, an etching process (KOH) or a SMART CUT process; a process comprising a H2 implant and anneal.
According to conventional complimentary metal oxide semiconductor (CMOS) fabrication techniques, the reduction of the depletion layer thickness is realized by a super-steep retrograded well (SSRW) ion implantation process. However, this process is limited by the diffusion of dopant atoms during subsequent thermal processes (e.g., annealing).
Conventional SOI-type devices include an insulative substrate attached to a thin film semiconductor substrate which contains transistors similar to the MOSFET described with respect to bulk semiconductor-type devices. The transistors have superior performance characteristics due to the thin film nature of the semiconductor substrate and the insulative properties of the insulative substrate. The superior performance is manifested in superior short channel performance (i.e., resistance to process variation in small size transistor), near-ideal subthreshold voltage swing (i.e., good for low off-state current leakage), and high saturation current.
Silicon on insulator (SOI) devices have been dubbed as the next successor to the reigning Complementary Metal On Silicon (CMOS) devices. Silicon on insulator (SOI) has excellent isolation properties. Silicon on insulator (SOI) has existed for almost two decades, but still improved methods for making silicon on insulator (SOI) devices are needed to advance the technology.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 4,169,000(Riseman) shows a STI air gap and a wafer bonded thereover. U.S. Pat. No. 6,084,271(Yu et al.) shows a silicon on insulator (SOI) process with wafer bonding and shallow trench isolation (STI). U.S. Pat. No. 5,988,292(Black et al.) teaches a method to join multiple wafer using STI and wafer bonding. U.S. Pat. No. 5,985,728(Jennings) shows a SOI process with wafer bonding and a boron layer. U.S. Pat. No. 6,013,936(Colt, Jr.) teaches a double SOI device. U.S. Pat. No. 5,484,738(Chu et al.) teaches a Bonded SOI device/process.
It is an object of the present invention to provide a method to form a silicon on insulator (SOI) device.
It is an object of the present invention to provide a method to form a silicon on insulator (SOI) device that uses wafer bonding technique.
It is an object of the present invention to provide a method to form a silicon on insulator (SOI) device that uses wafer bonding technique that can be use to form fully and partially depleted complementary devices.
It is another object of the invention to provide a method to form a silicon on insulator device that uses wafer bonding techniques that can be used to make fully and partially depleted complementary devices with optional air gaps in insulating regions.
To accomplish the above objectives, the present invention provides a method of manufacturing a SOI device.
A first substrate is provided having trenches in a first side. The first substrate has a second side. A first insulating layer is formed over the first side of the first substrate and filling the trenches. We planarize the first insulating layer to from isolation regions (e.g., STI). The three embodiments of the invention planarize the first insulating layer to different levels. In the second embodiment, the first insulating layer is etched back to form a recess. This recess later forms an air gap. We provide a second substrate having a second insulating layer over a first side of the second substrate. The second substrate has a second side. We bond the second insulating layer to the first insulating layer. Next, we thin the first substrate from the second side to expose the first insulating layer to form active areas between the isolation regions. Lastly, devices are formed in and on the active areas.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.